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7-4

DQ/DQS Bus Mode Pins for Stratix V Devices

SV51008

2014.01.10

Figure 7-1: DQS Pins in Stratix V I/O Banks

This figure shows the DQ/DQS groups numbering in a die-top view of the device where the numbering

scheme starts from the top-left corner of the device going clockwise.

DLL_TL

DQS1T

DQS66T

DLL_TR

8A

8B

8C

8D

8E

7E

7D

7C

7B

7A

Stratix V Device

3A

3B

3C

3D

4E

4D

4C

4B

4A

DLL_BL

DQS62B

DQS1B

DLL_BR

DQ/DQS Bus Mode Pins for Stratix V Devices

The following table list the pin support per DQ/DQS bus mode, including the DQS/CQ and DQSn/CQn

pins. The maximum number of data pins per group listed in the table may vary according to the following

conditions:

? Single-ended DQS signaling — the maximum number of DQ pins includes parity, data mask, and QVLD

pins connected to the DQS bus network.

? Differential or complementary DQS signaling — the maximum number of data pins per group decreases

by one. This number may vary per DQ/DQS group in a particular device. Check the pin table for the

exact number per group.

? DDR3 and DDR2 interfaces — the maximum number of pins is further reduced for an interface larger

than x8 because you require one DQS pin for each x8/x9 group to form the x16/x18 and x32/x36 groups.

Altera Corporation

External Memory Interfaces in Stratix V Devices

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